Computer processors comprise arithmetic, logic, and control circuitry that interpret and execute instructions from a computer program. Referring to FIG. 1, a typical computer system includes a microprocessor (22) having, among other things, a CPU (24), a system controller (26), and an on-chip cache memory (30). The microprocessor (22) is connected to external cache memory (32) and a main memory (34) that both hold data and program instructions to be executed by the microprocessor (22). Internally, the execution of program instructions is carried out by the CPU (24). Data needed by the CPU (24) to carry out an instruction are fetched by the memory controller (26) and loaded into internal registers (28) of the CPU (24). Upon command from the CPU (24) requiring memory data, the fast on-chip cache memory (30) is searched. If the data is not found, then the external cache memory (32) and the slow main memory (34) is searched in turn using the memory controller (26). Finding the data in the cache memory is referred to as a xe2x80x9chit.xe2x80x9d Not finding the data in the cache memory is referred to as a xe2x80x9cmiss.xe2x80x9d
The time between when a CPU requests data and when the data is retrieved and available for use by the CPU is termed the xe2x80x9clatencyxe2x80x9d of the system. If requested data is found in cache memory, i.e., a data hit occurs, the requested data can be accessed at the speed of the cache and the latency of the system is reduced. If, on the other hand, the data is not found in cache, i.e., a data miss occurs, and thus the data must be retrieved from the external cache or the main memory at increased latencies.
In computer and information processing systems, various integrated circuit chips must communicate digitally with each other over common buses. The receiving bus nodes recognize the signal as being high or low using receivers, also referred to as input buffers. Often the receiver is a differential receiver, i.e., a receiver that detects the difference between two input signals, referred to as the differential inputs. These input signals may be a received signal and a reference voltage or they may be a received signal and the inverse of the received signal. In either case, it is the difference between the two input signals that the receiver detects in order to determine the state of the received signal.
Integrated circuits are powered at certain voltage levels, which levels are then provided to the various components, such as the receivers, which are located on the integrated circuit. However, the nominal supply voltage for integrated circuits keeps being decreased to reduce power consumption. Additionally, fluctuations of the voltage level during operation can make the voltage level powering a receiver even lower. The lower the supply voltage, the more challenging it is to get a receiver to operate reliably. Often the operating voltage for the circuit must be generated from a low voltage power supply, e.g., a battery. In order to produce the variance in voltage required by circuit components from these low voltage power supplies, voltage multipliers are used. Typical voltage multipliers consist of diodes coupled across capacitors such that the input voltage is increased every half cycle or full cycle depending on configuration.
In general, in one aspect, the present invention involves a voltage multiplier comprising a first stage for receiving an input voltage and a first control signal; inverting the first control signal to produce a second control signal; and outputting a first output voltage and the second control signal. The voltage multiplier further comprises a second stage for receiving the first output voltage and the second control signal; and outputting a third output voltage. The first output voltage is higher than the input voltage and the second output voltage is higher than the first output voltage.
In general, in one aspect, the present invention involves a method of multiplying voltage comprising receiving, in a first stage, an input voltage and a first control signal; inverting, in the first stage, the first control signal to produce a second control signal; and outputting, from the first stage, a first output voltage and a second control signal. The method further comprises receiving, in a second stage, the first output voltage and the second control signal; and outputting a second output voltage. The first output voltage is higher than the input voltage and the second output voltage is higher than the first output voltage.
In general, in one aspect, the present invention involves a voltage multiplier comprising means for receiving, in a first stage, an input voltage and a first control signal; means for inverting, in the first stage, the first control signal to produce a second control signal; and means for outputting, from the first stage, a first output voltage and a second control signal. The voltage multiplier further comprises means for receiving, in a second stage, the first output voltage and the second signal; and means for outputting a second output voltage. The first output voltage is higher than the input voltage and the second output voltage is higher than the first output voltage.
In general, in one aspect, the present invention involves a voltage multiplier comprising a stage that comprises a first inverter for inverting an input voltage; a first transistor; a second transistor; a third transistor; a fourth transistor; a first capacitor; and a second capacitor. The first transistor has a gate and a drain tied together and coupled to a pull-up voltage; and a source coupled to a source of the second transistor. The first capacitor is coupled between the first inverter and the connection of the source of the first transistor and source of the second transistor. The second transistor has a bulk and a source tied together; a drain coupled to a drain of the third transistor; and a gate coupled to a gate of the third transistor and the input voltage. The third transistor has a source coupled to ground. The second capacitor is coupled between a gate of a fourth transistor and the connection between the drain of the second transistor and the drain of the third transistor. A drain of the fourth transistor is coupled to the gate of the fourth transistor. A source of the fourth transistor provides an output voltage.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.